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MATRIX7878's avatar
MATRIX7878
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
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Where are the example files

Hello, I generated a few examples in Verilog (as VHDL was not an option) for EMIF, PCIe and a few others. I opened up the .qsf file and I see all the IP's being used, but I cannot find a top-l...
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  • sstrell's avatar
    sstrell
    2 years ago

    Didn't realize that about the HDL selection. VHDL probably coming in a future version.

    The whole point of an IP is that it isolates you from these details. All you need to do is use the programming model for the IP (either at the hardware level with register access or at the software level with macros created using software tools) to read and write the memory. And again, since most of the interface in newer devices is hardened, the only HDL code you will see is the implementation of the Avalon or AXI connection to the hard IP.

    As far as a processor is concerned, if you are talking about the HPS in an SoC device, rocketboards.org is the place to go for examples.

    If you are looking at learning the details of signaling between the FPGA and the external memory, download a spec sheet from Micron or any memory manufacturer. Very detailed explanations on how everything works.

MATRIX7878's avatar
MATRIX7878
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hello,

Alright I see. I was creating a whole project for the device, not just the part I want. For the Generate HDL, that does have VHDL, the generate design EXAMPLE does not. That is only Verilog. I do now see the instantiated top-level file. I am hoping that the whole DDR protocol is somewhere also. I see the instantiation file in .vhd, but do not see any other .vhd files. Where are the other files that I will need? I am trying to learn the protocol.

Thank you,

Drew

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
2 years ago

The HDL option for the example design is right in the screenshot you attached. First option on the Example Design tab.

What "other files" are you looking for? It's not clear what you need at this point. If you are saying that you want to try to understand how an EMIF works by going through the HDL for the IP, that isn't really going to help much because most of the interface is hardened.