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Altera_Forum
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10 years ago

Weird LVDS output assignment error

I have a 14-bit LVDS output feeding a DAC samples. The output assignments being used have been used in several other designs (I exported the assignments and imported them into a new project).

Recently, I added a MUX which selects the output value based on whether the clock synchronous to the output samples is high or low. After adding this MUX, I started to get two errors regarding the LVDS output assignments:

1) Pin <name> is assigned to location <name> and pin <name> is assigned to location <name>. These two pins form a differential pair. However, these two locations do not belong to the same differential pair.

and

2) Error: can't place differentialI/O negative pin at a differential I/O positive location

These two error messages refer to only 2 bits of the LVDS output driver (the first and last pins of the bus.)

If I remove the MUX from the design and hard code the output to one of the possible sample sources, no error occurs. If I add the MUX back selecting between the two sample sources, I get the errors. If I keep the MUX but hard code one of the selections to a specific value, I do not get the error.

From the error (1) it appears as though Quartus mistakenly believes that the output pins (named HSTC_TX[0] and HSTC_TX[13]) are part of a differential pair, when they are not. I am not sure why it would assume this, since the assignments explicitly shows the correct LVDS_E_1R output pairs as HSTC_TX[0](n) and HSTC_TX[13](n). I believe that (2) is a result of it trying to mistakenly choose HSTC_TX[13] as the negative pair of HSTC_TX[0].

I am honestly confused since the exact same assignments have worked in other designs. I have checked the QSF file line by line, and it appears to be correct. Why would the logic synthesized be affecting the fitter like this?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    --- Quote Start ---

    Which device are you using and are you using ALTLVDS?

    --- Quote End ---

    Thank you for your reply!

    1) It is a Stratix III 3SL150 1152.

    2) I am not using the ALTLVDS component; the LVDS signals are being driven (single endedly) by the output of a sample generator on the FPGA. The complement pins are being inferred by the fitter.

    The exact errors I get are:

    Pin HSTC_TX[0] is assigned to location AE8 (PAD_AE8) and pin HSTC_TX[13] is assigned to location AE15 (PAD_AE15). These two pins form a differential pair. However, these two locations do not belong to the same differential pair.

    Can't place differentialI/O negative pin HSTC_TX[13] at a differential I/O positive location AE15 (PAD_AE15).

    As an example, the following code gives the error: 

    
P_OUTSEL : PROCESS(ALL)
BEGIN
  HSTC_TX <= sample_a;
  IF( clk = '1' ) THEN
    HSTC_TX <= sample_b;
 END IF;
END PROCESS;

    This code does NOT give the error: :confused: 

    
P_OUTSEL : PROCESS(ALL)
BEGIN
  HSTC_TX <= sample_a;
  IF( clk = '1' ) THEN
    HSTC_TX <= (OTHERS=>'0');
 END IF;
END PROCESS;

    Also, the fitter assignments correctly lists HSTC_TX[0] at PIN_AE8, and HSTC_TX[0](n) at PIN_AE7 and HSTC_TX[13] at PIN_AE15 and HSTC_TX[13](n) at PIN_AF15.

    Is there any logic-level reason or naming-convention reason that the tool would think these two outputs are differential pairs when their locations are not?

    Thank you.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    So after further investigation, the error seems to occur due to the MSb , HSTC_TX[13].

    If I get rid of the pin by assigning it to a constant, the fitter error goes away!

    ,

    From the RTL view, the proper MUX structure is being inferred, but for some reason the fitter must think that the generated netlist for this output is supposed to be differentially related!

    Another weird observation, is that the LSb being driven by the signal is always the one in conflict with the fitter. If I were to just tie HSTC_TX[0] to GND, the error would be with HSTC_TX[1]. If I were to tie HSTC_TX[1:0] to GND, the error would be with HSTC_TX[2].

    At this point I am extremely confused.

    EDIT: It has to be netlist related, since if I negate the one bit (HSTC_TX[13]), the error goes away. For some reason the fitter is looking at my logic, assuming that these pins are supposed to be differentially related, and then complaining when the pin out does not assign them to the same differential pair outputs.