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Which device are you using and are you using ALTLVDS?
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Thank you for your reply!
1) It is a Stratix III 3SL150 1152.
2) I am not using the ALTLVDS component; the LVDS signals are being driven (single endedly) by the output of a sample generator on the FPGA. The complement pins are being inferred by the fitter.
The exact errors I get are:
Pin HSTC_TX[0] is assigned to location AE8 (PAD_AE8) and pin HSTC_TX[13] is assigned to location AE15 (PAD_AE15). These two pins form a differential pair. However, these two locations do not belong to the same differential pair.
Can't place differentialI/O negative pin HSTC_TX[13] at a differential I/O positive location AE15 (PAD_AE15).
As an example, the following code gives the error:
P_OUTSEL : PROCESS(ALL)
BEGIN
HSTC_TX <= sample_a;
IF( clk = '1' ) THEN
HSTC_TX <= sample_b;
END IF;
END PROCESS;
This code does NOT give the error: :confused:
P_OUTSEL : PROCESS(ALL)
BEGIN
HSTC_TX <= sample_a;
IF( clk = '1' ) THEN
HSTC_TX <= (OTHERS=>'0');
END IF;
END PROCESS;
Also, the fitter assignments correctly lists HSTC_TX[0] at PIN_AE8, and HSTC_TX[0](n) at PIN_AE7 and HSTC_TX[13] at PIN_AE15 and HSTC_TX[13](n) at PIN_AF15.
Is there any logic-level reason or naming-convention reason that the tool would think these two outputs are differential pairs when their locations are not?
Thank you.
Honored Contributor
