Ways to improve timing on Top module?

Do you have registers on the boundaries of your partitions? If you don't, then paths in the top level may become critical. Remember that there is no optimization across partition boundaries, so combinational logic on the boundaries of the design partitions cannot be optimized with respect to the top level.

Adding registers at the boundaries can fix this, allowing you to run the design faster at the expense of an extra cycle of latency.

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