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Altera_Forum's avatar
Altera_Forum
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15 years ago

Warnings VHDL

Hi!!!!

Can you help me? I do not understand because they give me these mistakes. That happens??

It is a door of a bank detector of metals.

I´m spanish girl, I sit(feel) my bad way of expressing

Sorry!!

Kiss

library ieee;

use ieee.std_logic_1164.all;

entity puerta is

port(clk, reset: in std_logic;

presencia, metal, abrir: in std_logic;

entrada, salida, led: out std_logic);

end puerta;

architecture uno of puerta is

type estado is(abriendo, cerrando, abierto, cerrado, metal_ON);

signal actual, siguiente: estado;

begin

process(clk,reset)

begin

if reset= '0' then

actual <= abierto;

elsif clk'event and clk = '1' then

actual <= siguiente;

end if;

end process;

process (actual, presencia, metal, abrir)

begin

siguiente <= actual;

case actual is

when abierto =>

entrada <= '1';

salida <= '0';

led <= '0';

if presencia = '1' then

siguiente <= cerrando;

else

siguiente <= abierto;

end if;

when cerrando =>

entrada <= '0';

if metal = '1' then

siguiente <=metal_ON;

else

siguiente <= abriendo;

end if;

when metal_ON =>

led <= '1';

if abrir = '1' then

siguiente<=abriendo;

else

entrada <='1';

siguiente <= abierto;

end if;

when abriendo =>

led <= '0';

salida <= '1';

if presencia = '1' then

siguiente <= abriendo;

else

siguiente <= cerrado;

end if;

when cerrado =>

salida <= '0';

entrada <= '1';

siguiente <= abierto;

end case;

end process;

end uno;

library ieee;

use ieee.std_logic_1164.all;

entity temporizador is

port(clk, reset: in std_logic;

duracion: in std_logic_vector(15 downto 0);

carga_apertura, carga_cierre: in std_logic);

end temporizador;

architecture dos of temporizador is

type estado is(abriendo, cerrando, abierto, cerrado, metal_ON);

signal actual, siguiente: estado;

begin

process(clk,reset)

begin

if reset= '0' then

siguiente <= abierto;

elsif clk'event and clk = '1' then

if duracion = "0000000000000000" then

actual <= abierto;

elsif duracion = "0110000110101000" then

if carga_cierre ='1' then

actual <= cerrando;

end if;

elsif duracion = "0011101010011000" then

if carga_apertura ='1' then

actual <= abriendo;

end if;

elsif duracion = "0010011100010000" then

if carga_apertura ='1' then

actual <= abriendo;

end if;

else

actual <= abierto;

end if;

end if;

end process;

end dos;

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    You get an "inferring latches" warning, because you don't set all existing output ports for all states of your Moore state machine. Assign values of '1' or '0' to any output for each state below "case actual".

    The second entity in your file can't implement any logic behaviour, because it hasn't (yet) outputs.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Please, one finalizes question: since I can solve this?

    Almost I have obtained it, only I lack two latchs

    Warning: Found pins functioning as undefined clocks and/or memory enables

    Info: Assuming node "clk" is an undefined clock

    and...

    Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family

    Thanks.