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Altera_Forum
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16 years ago

Warnings VHDL

Hi!!!! Can you help me? I do not understand because they give me these mistakes. That happens?? It is a door of a bank detector of metals. I´m spanish girl, I sit(feel) my bad way of expre...
Altera_Forum's avatar
Altera_Forum
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16 years ago

You get an "inferring latches" warning, because you don't set all existing output ports for all states of your Moore state machine. Assign values of '1' or '0' to any output for each state below "case actual".

The second entity in your file can't implement any logic behaviour, because it hasn't (yet) outputs.