Warning: Output pins are stuck at VCC or GND

I am getting the following warning which is giving me an incorrect output.

Warning: Output pins are stuck at VCC or GND

I am just a beginner at VHDL, request help to rectify the problem.

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity norgate is

port(

a : in STD_LOGIC;

b : in STD_LOGIC;

c : out STD_LOGIC

);

end;

architecture Behave of norgate is

begin

c <= a NOR b ;

end ;

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity andgate is

port(

x,y,z : in STD_LOGIC;

f : out STD_LOGIC

);

end;

architecture Behave of andgate is

begin

f <= x AND y AND z ;

end ;

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity flipflop is

port (

j,k,clock : in STD_LOGIC;

q , qn : buffer STD_LOGIC );

end flipflop;

architecture structure of flipflop is

component norgate is

port(

a : in STD_LOGIC;

b : in STD_LOGIC;

c : out STD_LOGIC);

end component;

component andgate is

port(

x : in STD_LOGIC;

y,z : in STD_LOGIC;

f : out STD_LOGIC);

end component;

signal temp1,temp2: std_logic;

begin

and1: andgate PORT MAP ( j,clock , qn , temp1 );

and2: andgate PORT MAP ( k,clock , q , temp2 );

nor1: norgate PORT MAP ( temp1 , qn , q );

nor2: norgate PORT MAP ( temp2 , q , qn );

end structure;