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Altera_Forum
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12 years ago

Warning: Output pins are stuck at VCC or GND

I am getting the following warning which is giving me an incorrect output. Warning: Output pins are stuck at VCC or GND I am just a beginner at VHDL, request help to rectify the problem. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Due to wrong circuit, output doesn't depend on inputs and logic completely removed in design optimization. Flip q and qn connection to AND gates.

The circuit would be correctly named JK latch rather than JK flip-flop because it's level sensitive.