Forum Discussion
Warning (13028): Removed fan-out from the always-disabled I/O buffer....
- 2 years ago
So what is the issue and your goal at this point? You have disabled tri-state buffers that are not being used in the design.
Also, it should be mentioned that there is no tri-state logic internal to the FPGA fabric, only in the I/O cells, so that may be part of the issue here as well. Note "I/O buffer" in the warning.
If you are trying to determine what resources are being used and what has been removed, use the Technology Map Viewer (Post-fitting) to see a schematic of the used device resources post-fit.
You don't show what is controlling that other input into the NAND gate. If it can toggle, then the control logic for the buffers must remain, but that doesn't seem to be the case here.
Built-in help clarifies what is happening: https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#msgs/msgs/wmls_opt_removed_fanin_from_always_disabled_io_buf_to_tri_bus_hdr.htm
If DI_INT_CS4_ is always logic high, the output of the NAND gate will always be high no matter what the logic state of the other input is. Therefore, I wouldn't think the other input would matter.
Also, the built-in help says the following about the warning: