Forum Discussion
New ContributorWarning (13028): Removed fan-out from the always-disabled I/O buffer....
So what is the issue and your goal at this point? You have disabled tri-state buffers that are not being used in the design.
Also, it should be mentioned that there is no tri-state logic internal to the FPGA fabric, only in the I/O cells, so that may be part of the issue here as well. Note "I/O buffer" in the warning.
If you are trying to determine what resources are being used and what has been removed, use the Technology Map Viewer (Post-fitting) to see a schematic of the used device resources post-fit.
Super ContributorIf DI_INT_CS4_ is pulled up, the output of that NAND gate will always be high so the buffers will never be active. You should ground that signal and control the other signal into that NAND gate to activate (or deactivate) the buffers.
As for splitting the design between two devices, you need two Quartus projects to do this anyway, so just delete what shouldn't be in one device or the other.
sth125I had thought connecting Vcc to DI_INT_CS4_ would make sure the logic got removed.
What exactly does "Removed fan-out from the always-disabled " mean. What is being removed? Is it just removing the output connections of the two 74541 Octal Buffers and leaving the 74541s and other input logic in the generated logic?It would be nice to keep the design as it is now. If not I will change them, but I would like to know what is being generated for the existing design.
