Wait Statement must contain condition
Hello,
I am very new to FPGA and VHDL etc... I am trying to get my first code to work on Quartus Prime Lite in VHDL. It is a simple "Hello World" code (see below).
entity VHDLTuto is
end entity;
architecture sim of VHDLTuto is
begin
process is
begin
report "Hello World!";
wait;
end process;
end architecture;
I get the following error :
Error (10533): VHDL Wait Statement error at VHDLTuto.vhd(11): Wait Statement must contain condition clause with UNTIL keyword
I haven't found any reason for this error to appear. Is it a problem when creating the project? Or is it a problem when installing the software ?
Any help would be highly appreciated.
Thank you
You're trying to compile in Quartus, which is trying to synthesize the design into hardware, which is the goal of the compiler. If you want to just run simulations, you have to compile and run the sim in a simulation tool, like ModelSim or Questasim.