Forum Discussion
LeaG
New Contributor
New ContributorWait Statement must contain condition
Hello,
I am very new to FPGA and VHDL etc... I am trying to get my first code to work on Quartus Prime Lite in VHDL. It is a simple "Hello World" code (see below).
entity VHDLTuto is end entity;...
You're trying to compile in Quartus, which is trying to synthesize the design into hardware, which is the goal of the compiler. If you want to just run simulations, you have to compile and run the sim in a simulation tool, like ModelSim or Questasim.
LeaGNew Contributor
New ContributorThank you for your reply.
Ok if I understood correctly my error comes from the fact that my code would not work on an actual hardware.
I am following this tutorial : https://vhdlwhiz.com/basic-vhdl-tutorials/
And since I don't have any hardware I was just trying to do simulations. From the tutorial the "wait until" doesn't seem to be an issue. Why so? Do I need to do an extra step?
Thank you in advance
Ok if I understood correctly my error comes from the fact that my code would not work on an actual hardware.
I am following this tutorial : https://vhdlwhiz.com/basic-vhdl-tutorials/
And since I don't have any hardware I was just trying to do simulations. From the tutorial the "wait until" doesn't seem to be an issue. Why so? Do I need to do an extra step?
Thank you in advance
sstrell
Super Contributor
Super ContributorYou're trying to compile in Quartus, which is trying to synthesize the design into hardware, which is the goal of the compiler. If you want to just run simulations, you have to compile and run the sim in a simulation tool, like ModelSim or Questasim.
- LeaGHallelujah! I understand now, my bad I got mixed up with the softwares. Thank you very much this will help me a lot!
