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LeaG's avatar
LeaG
Icon for New Contributor rankNew Contributor
4 years ago
Solved

Wait Statement must contain condition

Hello, I am very new to FPGA and VHDL etc... I am trying to get my first code to work on Quartus Prime Lite in VHDL. It is a simple "Hello World" code (see below). entity VHDLTuto is end entity;...
  • sstrell's avatar
    sstrell
    4 years ago

    You're trying to compile in Quartus, which is trying to synthesize the design into hardware, which is the goal of the compiler. If you want to just run simulations, you have to compile and run the sim in a simulation tool, like ModelSim or Questasim.

RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
4 years ago

I’m glad that your question has been addressed. With that, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


Best Regards,

Richard Tan


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 9/10 survey.