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Altera_Forum's avatar
Altera_Forum
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10 years ago

vital glitch in my clock pattern.

hi team,

i generated a clock pattern using Libero software.but after post layout simulation .vital glitches are coming.i dont know how to remove it??

this is the code i written and testbench.please help me.

hi sir,

please help me sir. i need ur help. me a trainee in a small electronics company named synergy in kerala.they gave a task to generate a waveform.i wrote vhdl program . after post layout simulation,i got vital glitch. i dont know how to remove this in actel libero. please help me.

top .docx : main program

aaaaaa.docx: testbench

untiled jpg : image after first simulation means..what is the expected output

glitch jpg: final image output but not coorct because of glitch problem.

after checking my program can u give your valuable suggestions to avoid vital glitch?????????

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Its probably because your counter changes on the falling edge, and the state machine changes on the rising edge of the clock. Any reason why you did this? did you provide an SDC file that accounted for this half-clock cycle timing relationship?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    helo sir i included the image in pdf format. sir,please

    go through my program and please tell me where is the orgin of vital glitch...i am doing simulation in modelsim actel libero.