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Honored Contributor
Honored Contributorvital glitch in my clock pattern.
hi team, i generated a clock pattern using Libero software.but after post layout simulation .vital glitches are coming.i dont know how to remove it?? this is the code i written and testbench.p...
Altera_ForumHonored Contributor
Honored ContributorIts probably because your counter changes on the falling edge, and the state machine changes on the rising edge of the clock. Any reason why you did this? did you provide an SDC file that accounted for this half-clock cycle timing relationship?
