Virtual clock or Real Clock?

Virtual clock is meant for input delay use. It represents the launch clock of external device registers inputting to the fpga.

How about the set output delay? should i use virtual clock or real clock?

Use output real clock as ref for set_output_delay. This is the clock that goes out with data.

I suggest to use the manual at the following link

The -clock option for the set_output_delay SDC constraint is used to specify the external capture clock of an output(s) from the FPGA. There are typically 3 cases involved with specifying which clock to use. The first case (1) is when the capture clock is a clock generated (output) from the FPGA. This is a 'real' generated clock usually with a target of an output port, and is used for source synchronous interfaces. The next case (2) is when the capture clock is the same as a clock feeding the FPGA. This is a 'real' absolute clock (create_clock), and is used for system synchronous interfaces. The last case (3) is similar to the previous one, however the capture clock is a virtual clock. A virtual clock has no target in the FPGA, but must be related to the source clock. This can be achieved with the -waveform option on the create_clock statement for the virtual clock, or the skew between them can be specified using the set_clock_latency constraints. This is the recommended method. The other advantage of using the virtual clock is that the jitter on this clock can be specified independently from the input jitter of the source clock using the set_clock_uncertainty command. This could be useful if the source clock feeds a PLL, which may filter out much of the input clock jitter.