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Altera_Forum
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15 years ago

Virtual clock or Real Clock?

Hi. I am confused on the using virtual clock or real clock for the set_output_delay? Different articles have different opinion. Article like: Best Practices for the Quartus II TimeQuest...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Virtual clock is meant for input delay use. It represents the launch clock of external device registers inputting to the fpga.

The actual input clock will be phase shifted from virtual clock due to board delay.