Honored ContributorHi,
I am quite new to VHDL and Quartus II. I have coded a 16x8 RAM using VHDL in Quartus but I don't know how to check it because I cannot view the array variable where the data is stored in waveform simulation. Is there anyway I can check the contents of the array..? Maybe by other means..? Please advice.. Thanks..
Honored ContributorWhat simulation tool are you using? In most simulation programs you can set which format you want to view data in, an array can be handy to show in hex for example.
//OlaHonored ContributorThanks for the reply..
I am using Functional Simulation. I have heard of testbenches but don't really know how to use it.. What I hope to achieve is to be able to know what data is actually written into and stored in the array when data is written through the Data pins (declared as "inout std_logic_vector (7 downto 0)") during the writing process and, to be able to view the data output through the Data pins during reading process.Honored ContributorYour problems sounds quite simple, there must be an easy way to display arrays, but since I've never used the altera simulation I can't help you there.
I've looked around here on the forum before and people tend to think that modelsim has many advantages. If you like I can send you a design file with corresponding test bench and a do file. Just reply with your email. What you then is to start a modelsim project, compile the file and write "do <file.do>". Very simple. //OlaHonored ContributorYes please..
I've already PMed u the email.. Thanks..Honored ContributorHi mrnobody,
I don't know if I understood well your problem, anyway seems similiar to what I had: I wanted to "check" internal signals with a Vector Waveform File. Now I do this: simply define a extra output port in my entity, and connect it to the signal I wanted to do. This is useful also when I use SignalTap analyzer. For example (just the shortest piece of VHDL code, if needed I can post more): romprobe <= romout ; -- STII / VWF signal where romout is the "real" output of my ROM, and romprobe is the "extra" port as described above. hope this helps, CHonored ContributorWell..
Below is the RAM code that I've done in VHDL.
library ieee;
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
entity RAM is
port ( A0,A1,A2,A3 : in std_logic;
CS : in std_logic;
clk : in std_logic;
R_Wbar : in std_logic;
Data : inout std_logic_vector (7 downto 0);
DataOut : out std_logic_vector (7 downto 0)); -- for testing
end RAM;
Architecture version1 of RAM is
signal Addr : unsigned (3 downto 0);
type MEM is array (15 downto 0) of std_logic_vector (7 downto 0);
signal MEM_s : MEM;
Begin
Addr <= (A0 & A1 & A2 & A3);
Process (clk)
variable Addr_int : integer;
Begin
if Rising_Edge(clk) then
Addr_int := TO_INTEGER(Addr);
if (CS = '0') then
if (R_Wbar = '0') then
MEM_s(Addr_int) <= Data;
DataOut <= MEM_s(Addr_int);
elsif (R_Wbar = '1') then
Data <= MEM_s(Addr_int) ;
DataOut <= Data;
end if;
end if;
end if;
End process;
End version1;
Bango:
I've downloaded ModelSim and tried it. It seems similar to the waveform simulator in Quartus i guess. cirutech: I've only tried Vector Waveform File simulator in Quartus. However, I am very keen in learning how to use SignalTap if that can help me in learning VHDL. Do you know of a good tutorial that I can follow..? Preferably one that explains by example.. Thanks..Honored ContributorIn the megawizard you can instantiate ram blocks so you don't need to write them yourself. Try that, could be something in the code.
//OlaHonored ContributorHonored Contributor
