Viewing variable values in VHDL

Hi mrnobody,

I don't know if I understood well your problem, anyway seems similiar to what I had: I wanted to "check" internal signals with a Vector Waveform File.

Now I do this: simply define a extra output port in my entity, and connect it to the signal I wanted to do. This is useful also when I use SignalTap analyzer. For example (just the shortest piece of VHDL code, if needed I can post more):

romprobe <= romout ; -- STII / VWF signal

where romout is the "real" output of my ROM, and romprobe is the "extra" port as described above.

hope this helps,

C