Video Processing Suite SOPC creates Verilog for 1 block instead of VHDL

Hi y'all

I have SOPC builder Video Processing Suite project that is configured to create VHDL. There are maybe 8 or 9 blocks in there. When I generate they all create the necessary vhdl (and .vho) modules fine. I can build and simulate (modelsim PE), all is happy.

I added the 'switch' component in from the VIP suite (ver 9.1)

When I generate, for the 'switch' component, it creates verilog code for that block and that block only. The rest of the SOPC system is created using VHDL. Looking at the sopc file, it calls out vhdl for the switch.... I can still build OK in quartus, but don't have a PE verilog seat, so can't simulate to see why it doesn't work....

Any ideas? Is there only a verilog implementation of the 'switch' component? On the SOPC log it looks like it does something different... or have I got to hand $$$ to Mentor and get my PE upgraded to verilog?

Thanks