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Altera_Forum
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15 years ago

Video Processing Suite SOPC creates Verilog for 1 block instead of VHDL

Hi y'all I have SOPC builder Video Processing Suite project that is configured to create VHDL. There are maybe 8 or 9 blocks in there. When I generate they all create the necessary vhdl (and .v...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Pancake - thanks lots. I'll try sp2 out when I can... the thought of doing functional simulation at gate level ... uurrgggghhh