VHDL/Modelsim question (hard assignments)

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Hi experts - there must be an easy answer to this. For various reasons, in my code, and especially in my test bench, I have a lot (many dozens) of hard assignments (essentially gate-ROMs). If I just code them in-line, I have to scroll through lots and lots of line_xxxx when I browse for a signal in modelsim. But if I put all these hard assignments within a process(all), the simulator hangs(?). There's probably a better way to do this - what do you do?

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Since the contents of a ROM wouldn't change a single assignment to the signal would be all that is needed. I would code it like this...

 
process
begin
   a <= '1';
   b <= x0000";
   ... you get the point
 
   wait; -- Unconditional wait.  All of the signals have now been assigned
end process;

Kevin Jennings

Thank Kevin - what does the wait do? I never use those in RTL design coding - not sure what they're for, and Quartus often doesn't seem to like them.

thanks!

/j

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Thank Kevin - what does the wait do? I never use those in RTL design coding - not sure what they're for, and Quartus often doesn't seem to like them.

thanks!

/j

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Wait all by itself will wait forever, the process will permanently suspend. There are several flavors of wait statements...

wait; -- Unconditional, waits forever

wait until xxx; -- xxx is a boolean condition, such as 'rising_edge(clk)' or 'abc = '1'

wait for xxx; -- xxx is type time, such as 1 ns, 10 us

A process with a wait statement cannot be used with a sensitivity list, the compiler will flag it as an error for you to fix. Waits are more typically used in testbenches than synthesizable designs, however the following two forms are generally recognized as equivalent

 
process(clk)
begin
  if rising_edge(clk) then
    b <= a;
  end if;
end process;
 
process
begin
  wait until rising_edge(clk);
  b <= a;
end process;

Kevin Jennings

If you declare these signal in your tb, you could also initialize them at declaration.

constant rc_val     : natural := 67;
constant rom_cell   : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(rc_val, 8));