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Altera_Forum
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13 years ago

VHDL/Modelsim question (hard assignments)

Hi experts - there must be an easy answer to this. For various reasons, in my code, and especially in my test bench, I have a lot (many dozens) of hard assignments (essentially gate-ROMs). If I jus...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Thank Kevin - what does the wait do? I never use those in RTL design coding - not sure what they're for, and Quartus often doesn't seem to like them.

thanks!

/j