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Altera_Forum
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13 years ago

VHDL/Modelsim question (hard assignments)

Hi experts - there must be an easy answer to this. For various reasons, in my code, and especially in my test bench, I have a lot (many dozens) of hard assignments (essentially gate-ROMs). If I jus...
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Altera_Forum
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13 years ago

If you declare these signal in your tb, you could also initialize them at declaration. 

constant rc_val     : natural := 67;
constant rom_cell   : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(rc_val, 8));