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Altera_Forum's avatar
Altera_Forum
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12 years ago

VHDL Type Mismatch error at DorQ.vhd

Hi, I am trying to code for the following file DorQ.vhd but Quartus 2 keeps giving me an error of Error (10381): VHDL Type Mismatch error at DorQ.vhd(49): indexed name returns a value whose type does not match "std_logic_vector", the type of the target expression.

What might be the problem and how can I fix this.

Please remember that DorQ.vhd is the top level entity in the design.

Please post the full source code for DorQ.vhd if you manage to make it compile.

Thanks for your help and suggestions.

You will find the files attached.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Please consider the difference between the indexed name wire1(1) and the 1-bit wide slice name wire1(1 downto 1).

    All actual parameters of acff and bcff must be slice names.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Hi FvM. how do I code for the slice name wire1(1 down to 1). Could you please post the code as it would appear.

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    You'll use slice names where required by the formal, e.g. 

    ac1: acff port map (RIN, wire1(1 downto 1), wire0(1 downto 1), LIN);