VHDL to detrmine if 2 signals are drifting

Hi djstar,

Glad to see you are thinking!

A couple of comments;

The error in your pulse generation code is that you have not used the correct syntax for a clocked process. Kaz has corrected your HDL.

Note that Kaz's solution generates a combinatorial pulse. You could also have put that logic inside the process to generate a registered output, but in that case, you also need to initialize the value of the signals, eg.,

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mon_prescale is
  port (
    clk: in std_logic;
    monitor: in std_logic;
    mon_prescale: out std_logic
  );        
end entity;
architecture Behavioral of mon_prescale is
  -- Registers and their default values
  signal mon_delay: std_logic := '0';
  signal mon_out:    std_logic := '0';
begin
  process(clk)
  begin
    if rising_edge(clk) then
      mon_delay <= monitor;
      mon_out    <= monitor and (not mon_delay);
    end if;                        
  end process;
  mon_prescale <= mon_out;
end architecture;

Note how I have added two signals internal to your logic. The signal mon_out appears to be redundant, since you could have used mon_prescale directly, however, then you would not have been able to assign a default value to the signal. An FPGA will encode this default value in its configuration bit-stream.

A slight modification to this logic is to include a global reset signal (which in my opinion is a good idea)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mon_prescale is
  port (
    rstN: in std_logic;
    clk: in std_logic;
    monitor: in std_logic;
    mon_prescale: out std_logic
  );        
end entity;
architecture Behavioral of mon_prescale is
  -- Registers and their default values
  signal mon_delay: std_logic := '0';
  signal mon_out:    std_logic := '0';
begin
  process(clk, rstN)
  begin
    if (rstN = '0') then
      mon_delay <= '0';
      mon_out    <= '0';
    elsif rising_edge(clk) then
      mon_delay <= monitor;
      mon_out    <= monitor and (not mon_delay);
    end if;                        
  end process;
  mon_prescale <= mon_out;
end architecture;

In this case, when rstN asserts (I happen to have used an active low signal, but you can equally use active high) the outputs reset to zero.

If you never asserted rstN in your simulation, then the outputs would still be zero due to the initial values assigned when the signals were created.

Note: do not use the non-standard/deprecated libraries

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

instead use the standard library

use IEEE.NUMERIC_STD.ALL;

Also note that begin-entity and begin-architecture can be ended with end-entity and end-architecture as I have used in the code examples above. This makes it easier to copy and paste code, since you do not have to edit the entity or architecture name in two places if you've copied some code.

Cheers,

Dave