VHDL to detrmine if 2 signals are drifting

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Thanks for the reply guys, sorry am a bit late back replying I've had a dreaded cold!

I have had a start at writing a bit of code that detects the edge of a pulse which I have simulated and seems to work. The bit i'm stuck with is adding the portion of code that starts the counter. The edge detection output is called "mon_prescale" what I would like to do is when this signal goes hi start a counter. however when I use then if.... etc in the same process as the edge detector it throws up an error???

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mon_prescale is
    port (
        clk: in std_logic;
        monitor: in std_logic;
        mon_prescale: out std_logic
        
        );
        
end mon_prescale;
architecture Behavioral of mon_prescale is
    signal mon_delay: std_logic;
    
begin
    CounterProcess: process(clk)
    begin
        mon_prescale <= monitor and not mon_delay;
    
        if rising_edge(clk) then
            mon_delay <= monitor;
        end if;
                            
    end process;
    
    
end Behavioral;

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for edge detection I will do this:

  CounterProcess: process(clk)
    begin
        if rising_edge(clk) then
            mon_delay <= monitor;
        end if;
                            
    end process;
  mon_prescale <= monitor and not mon_delay;