VHDL Question

counter is a variable, so you should have := instead of <= like you did just above.

I'm afraid your code is completely broken and would not work in any language. A VHDL process is not the same as a verilog always@. You need to wait on the clk. sq_wave_reg is not a register.

2. +

4. -

Here is a sawtooth wave I found, i'm trying to get a 400Hz square wave, it compiles, any help will be appreciated. Thanks

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SquareWave is
port (clk : in std_logic; 
wave_out : out std_logic_vector(7 downto 0);
reset :in std_logic
);
end SquareWave;
architecture Behavioral of SquareWave is
signal count : integer := 0;
begin
process(clk,reset)
begin
if(reset = '1') then
count <= 0;
elsif(rising_edge(clk)) then
if(count = 10000000000) then
count <= 0;
else
count <= count + 1;
end if;
end if;
end process;
wave_out <= conv_std_logic_vector(count,8);
end Behavioral;

Check your warnings. You have "count" (a 32-bit integer) going to ten billion. This is not a sensible way to make sawtooth wave in any event.

search for books on this forum then you'll find recommendations

chjones2008, sorry if my comments came across as a bit terse. The intent was to be helpful. It's been a while, but I had a terrible time learning VHDL at first. The key for me, coming from C/C++, was understanding that VHDL is creating hardware and to think in terms of flip-flops and combinational logic. The two books that helped: