VHDL Question

I'm afraid your code is completely broken and would not work in any language. A VHDL process is not the same as a verilog always@. You need to wait on the clk. sq_wave_reg is not a register.

When do you expect "if (rst_n /= rst_n) then" to be true? You probably meant "if rst_n = '0' then"

You never change sq_wave_reg. You probably mean "sq_wave_reg <= not sq_wave_reg;"

Is this supposed to be synthesizable? Your comments say you want a 1 Hz wave from a 400 Hz clock. That means you should toggle every 200 clock cycles. Your CLOCK_FREQUENCY is meaningless.