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Altera_Forum's avatar
Altera_Forum
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11 years ago

vhdl programming synchronization issues

PLEASE DELETE this THREAD

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Your post is not well formatted and hard to read. Your code is also hard to follow. I dont think you really posted what the problem is.

    Where is the testbench for this code? and can you post the whole code? then people might be able to simulate it themselves.

    Did you know that VHDL supports base level primitives in the code? having your own components for each tends to lead to difficult to read and over-complicated code. Much easier to just write:

    a <= b xor c;

    etc.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    You still havent posted the code or the testbench. And it's still not clear exacltly what the problem is. I suspect there is a bug somewhere, but without the code, a clear explination of what it does, and a testbench, it is very difficult to comment.