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Altera_Forum's avatar
Altera_Forum
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15 years ago

[VHDL] Problem with 'event attribute on std_logic_vector signal

Hi all, i'm a newbie in vhdl coding and i'm trying to execute a vhdl code written by another person in quartus 2.

He has written it using Aldec Active HDL 8.2.This code in Active HDL compiles but not in Quartus 2.

Below I post the relevant code 


entity project is
         port(  IR:in std_logic_vector(7 downto 0);     
...
end project;
architecture arch of project is
...
control_logic_req: process (IR, other parameters)
if (IR 'event) then --error here
...

When i compile the code, i have an error on the row highlighted (there's also the ' but it doesn't appear in php window) and it's this one:

error (10302): vhdl attribute error at project.vhd(158): attribute "event" that is used for multiple bits is not synthesizable

Now i wonder

1) why it compiles in Active HDL and not in Quartus 2 with the same file .vhd? Does it need some additive library?

2) in quartus 2 how can i fix this problem?

Thanks everybody for your advices.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Quartus is synthesis tool and only supports the synthesis subset of vhdl.

    In this subset an edge event is translated to clocked flipflop. You can only have one clock per flip. So the clock signal must be one bit.

    If Aldec compiles it then you ned to know what is the outcome of compilation, it could be just simulation toolset.

    Anyway I advise you to write your own code. The worst thing is wasting time to port mystery codes across tools.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    the problem is that

    if IR'event then

    is perfectly legal VHDL, which is why it compiles in ActiveHDL (this ia just a simulator and development environment). It will work perfectly fine in a simulator. an event occurs any time IR changes. When it comes to Quartus, it has to map this behaviour on to real hardware, which it cannot do, as extra circuitry is required that detects changes in IR, that is not described in the VHDL. You would usually compare a registered version of IR to the current value of IR.

    Im guessing the origional designer intended it to be used in this way, but does not understand how hardware works.

    Edit - just to add, are you sure this isnt a VHDL model? its quite common to use VHDL like this in models rather than synthesisable code.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thank kaz and Tricky for your answers...

    Yes, it's a model and was not designed to be implemented on a specific hardware. I wanted to use Quartus 2 because this software is familiar to me (I used it with verilog).

    Is there a synthesizable way to code this part without using event attribute?
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    It really depends on what the code is doing. yes you probably can make it synthesisable, but if its a model using code like this elsewhere, it probably needs a complete re-write.