[VHDL] Problem with 'event attribute on std_logic_vector signal

Quartus is synthesis tool and only supports the synthesis subset of vhdl.

In this subset an edge event is translated to clocked flipflop. You can only have one clock per flip. So the clock signal must be one bit.

If Aldec compiles it then you ned to know what is the outcome of compilation, it could be just simulation toolset.

Anyway I advise you to write your own code. The worst thing is wasting time to port mystery codes across tools.