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Altera_Forum
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15 years ago

[VHDL] Problem with 'event attribute on std_logic_vector signal

Hi all, i'm a newbie in vhdl coding and i'm trying to execute a vhdl code written by another person in quartus 2. He has written it using Aldec Active HDL 8.2.This code in Active HDL compiles but ...
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Altera_Forum
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15 years ago

Thank kaz and Tricky for your answers...

Yes, it's a model and was not designed to be implemented on a specific hardware. I wanted to use Quartus 2 because this software is familiar to me (I used it with verilog).

Is there a synthesizable way to code this part without using event attribute?