jpt13653903New Contributor2 years agoVHDL Parser Access Violation on 64-bit decimal literals I have a VHDL-2008 file with the following line: constant TxFreqHz : std_logic_vector(63 downto 0) := 64d"3200000000"; -- 3.2 GHz This results in the following crash: Problem Details Error: ...Show More
Recent DiscussionsQuesta FPGA Starter Edition: Fatal WLF Error when restarting simSolvedMinimum pulse width violation on EMIF-HPSQuartus did not startA5EG013BB18A OPN is visible in Quartus but not listed in Program File GeneratorGenerate License by Activation Code Not Working