VHDL, MSF 5 bit counter

Hello everyone,

I'm an italian student, so I apologize for my english, and I'm new in

the forum, I have to do an exercise: the creation by MSF of a 5-bit

counter using VHDL.

I have various input signals: a STOP signal which stops the count at the

moment, a RESTART signal that resume the count, an UP_DOWN signal to

choose the direction of the count and the signal of RESET.

I have alse 3 output signals: a signal END_C which indicates the end of

the count, a signal START_C which indicates the start and a Q signal

which indicates the value of the count.

This is my VHDL code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity esercizio3 is
port(CK, stop, restart, reset, up_down: in std_logic;
       end_c, start_c: out std_logic;
      Q: out std_logic_vector(4 downto 0));
end esercizio3;
architecture arc of esercizio3 is
    type stato is(ST0, ST1, ST2, ST3);
    signal ps, ns: stato;
    signal temp: std_logic_vector(4 downto 0);
    begin
      seq_proc: process(CK, RESET)
       begin
        if(RESET='0')then
        ps<=ST0;
        elsif(rising_edge(CK)) then
        ps<=ns;
        end if;
      end process seq_proc;
      comb_proc:process(RESTART, STOP, UP_DOWN, PS)
      begin
      end_c<='0';
      start_c<='0';
       case ps is
       when ST0=>
         temp<="00000";
         if(stop='0')then
         ns<=ST0;
         elsif(up_down='0')then
         ns<=ST1;
         else
         ns<=ST2;
         end if;
      when ST1=>
        temp<=temp-"00001";
        if(stop='0')then
        ns<=ST3;
        elsif(up_down='0')then
        ns<=ST1;
        else
        ns<=ST2;
        end if;
     when ST2=>
        temp<=temp+"00001";
        if(stop='0')then
        ns<=ST3;
        elsif(up_down<='0')then
        ns<=ST1;
        else
        ns<=ST2;
        end if;
     when ST3=>
        if(Restart='1')then
        ns<=ST3;
        elsif(up_down='0')then
        ns<=ST1;
        else
        ns<=ST2;
        end if;
        when others=>
        ns<=ST0;
     end case;
     Q<=temp;
     if(temp="00000")then
     start_c<='1';
     elsif(temp="11111")then
     end_c<='1';
     end if;
   end process comb_proc;
end arc; 

The compilation is successful but I get an error in model sim which is:

# **Error: (vsim-3601) Iteration limit reached at time 15ns.

I suppose there is a loop that does not allow proper execution.

Can you help me fix it? Thanks you.