Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

VHDL, MSF 5 bit counter

Hello everyone, I'm an italian student, so I apologize for my english, and I'm new in the forum, I have to do an exercise: the creation by MSF of a 5-bit counter using VHDL. I have various...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Have the state machine generate a counter whale signal and another clocked process that describes the counter. There are plenty of examples out there for a clicked process with enable.