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jrrguzman's avatar
jrrguzman
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

VHDL model for ALTCLKCTRL not generated

Hi, I'm trying to simulate a design with an ALTCLKCTRL clock buffer in it. However, I can't get QSYS to generate the VHDL simulation model. It only does generate Verilog, not matter what settings I ...
jrrguzman's avatar
jrrguzman
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Hi,

Well the issue is not resolved since the tool does not generate the right component model. Yes, I get the .vhd file under simulation but not the right submodule which should be generated along. I wonder if you have tried to simulate the generated IP on Modelsim.

However I'm moving on since I am able to work with the simulation model from v18.0.

Thanks for the time.