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jrrguzman's avatar
jrrguzman
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

VHDL model for ALTCLKCTRL not generated

Hi, I'm trying to simulate a design with an ALTCLKCTRL clock buffer in it. However, I can't get QSYS to generate the VHDL simulation model. It only does generate Verilog, not matter what settings I ...
jrrguzman's avatar
jrrguzman
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Hi,

I made sure that was done but I can't make it nevertheless. It only generates the verilog counterpart which seems to have issues and can't be simulated either.

I'm using Quartus Prime Standard 17.0. Is there an issue for this in this particular version?

BTW, the simulation folder created is ./simulation/submodules

Cheers