VHDL latches

Hello,

I have a warnings in Quartus:

Warning (10631): VHDL Process Statement warning at dma.vhd(449): inferring latch(es) for signal or variable "din_exp", which holds its previous value in one or more paths through the process

Warning (10631): VHDL Process Statement warning at salsa_dma.vhd(449): inferring latch(es) for signal or variable "const_exp", which holds its previous value in one or more paths through the process

Suspicious code is looks like this:

SIGNAL din_exp, const_exp : STD_LOGIC_VECTOR(511 DOWNTO 0) ;
...
PROCESS(state, const, dout, ram_dout, data_in, din_exp, const_exp, din)
     VARIABLE din_exp_var, const_exp_var : STD_LOGIC_VECTOR(511 DOWNTO 0) ;     
    BEGIN
        CASE state IS
            WHEN idle_state => 
                
                din_exp_var := data_in(511 DOWNTO 0) XOR data_in(1023 DOWNTO 512) ;
                const_exp_var := data_in(511 DOWNTO 0) XOR data_in(1023 DOWNTO 512) ;                
                         
            WHEN s0_1 => 
                 din_exp_var := const XOR dout ;
                 const_exp_var := const XOR dout ;
        
            WHEN s1 => 
                 din_exp_var := din_exp ;
                 const_exp_var := const_exp ;
             -- other states 
            
            WHEN OTHERS =>
                 din_exp_var := const XOR dout ;
                 const_exp_var := const XOR dout ;    
    
        END CASE ;
        
        
             din_exp <= din_exp_var ;
             const_exp <= const_exp_var ;  
END PROCESS ;

In state s1 I don't want to change anything to my signal assignment, also previous values must be saved. There are no default values for these signals. Is there a latch needed? Is this code ok? Or should I change anything? How?

Thank you!