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Altera_Forum's avatar
Altera_Forum
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12 years ago

VHDL latches

Hello, I have a warnings in Quartus: Warning (10631): VHDL Process Statement warning at dma.vhd(449): inferring latch(es) for signal or variable "din_exp", which holds its previous value i...
Altera_Forum's avatar
Altera_Forum
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12 years ago

As I understand it, the two process style comes from the days when people (and tools) required separate processes for sequential logic and registers. And its a style thats never gone away. For beginners (and others) it is prone to latches.

Using a single clocked process removes these problems, and tools have no problems understanding them. I have no doubts you will get the same results with both (or if anything, you will get minor usage differences).

For me, a single process is more readible (and its all about readbility - not minor quibbles over 1 or 2 luts).