VHDL latches

When want a signal hold its value until some condition occurs, you should use register instead of latches. Registers needs a clock signal. You may modify your code this way:

process(clk,clr)

begin

if(clr='1') then

din_reg <= din_next;

elsif(clk'event and clk='1')then

end if;

end process;

PROCESS(...)

din_next <= din_reg;

BEGIN

CASE state IS

WHEN idle_state =>

din_next <= data_in(511 DOWNTO 0) XOR data_in(1023 DOWNTO 512) ;

WHEN s0_1 =>

din_next <= const XOR dout ;

WHEN s1 =>

din_next <= din_exp ;

WHEN OTHERS =>

din_next <= const XOR dout ;

END CASE ;

END PROCESS ;

The same for the rest of signals.