VHDL help with code

okey so tell me what is A1 A2 etc. Input or Output ? I have some code but i don't understand it... I really need this... Please help me ;c

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity projekt is

port(Up,Down, : in std_logic;

A0, A1, A2, A3: out std_logic);

end projekt;

architecture przerzutnik of projekt is

component T_FF is

port (T: in std_logic

Clock: in std_logic

Out: out std_logic);

signal tmp: std_logic;

begin

process (Clock)

begin

if Clock'event and Clock='1' then

if T='0' then

tmp <= tmp;

elsif T='1' then

tmp <= not (tmp);

end if;

end if;

end process;

Out <= tmp;

end przerzutnik;

begin

T_FF: T1 port map(T

T_FF: T2 port map

T_FF: T3 port map

T_FF: T4 port map