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Altera_Forum
Honored Contributor
Honored ContributorVHDL help with code
Hi! Can anyone help me ih writing VHDL code for this diagra? I need simulation results too. Thanks ! :))
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- --- Quote End --- Could you explain me how it works? I'm trying to write code in vhdl which will be works like this scheme, but I don't understand how to do it.
