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Altera_Forum's avatar
Altera_Forum
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10 years ago

VHDL Help Requested

Hello. I'm a VHDL newbie and request help on coding a counter. I'm trying to synchronize a BTRIG signal to the system clock and then toggle a short_long_sample_q signal every 4 synchronized BTRIG pulses. Here's the applicable section of code:

process ( SYS_CLK )

begin

if rising_edge ( SYS_CLK ) then

temp_pulse <= BTRIG ;

btrig_synched <= temp_pulse ;

end if ;

end process ;

process ( btrig_synched )

begin

if rising_edge ( btrig_synched ) then

btrig_counter <= btrig_counter + 1 ;

end if ;

end process ;

process ( btrig_counter , short_long_sample_q )

begin

if btrig_counter = "11" then

short_long_sample_q <= not short_long_sample_q ;

end if ;

end process ;

I don't get any compile errors but the tested behavior shows that short_long_sample_q does not consistently toggle every 4 BTRIGs. Is there a better way of coding this? Thanks.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Hello

    In your code the process controlling short_long_sample_q is asynchronous, which means that it will keep toggling this signal until btrig_counter is different than "11". This is possibly why you are experiencing strange behaviors.

    Make sure that SYSCLK > 2*BTRIG or else you will not be able to detect a rising edge on this signal

    I didn't test this code, but you can give it a try: 

    process ( SYS_CLK )
begin
if rising_edge ( SYS_CLK ) then
    if (btrig_previous = '0') and (BTRIG = '1') then -- Rising edge detected
         if (btrig_counter = "11") then -- Fourth rising edge detected
                  short_long_sample_q <= not short_long_sample_q;
                  btrig_counter <= "00";
         else 
                  btrig_counter <= btrig_counter + 1;
         end if
    end if
    btrig_previous <= BTRIG;
end if
end process
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    For the next time, please post your code in code tags. This makes it easier to read.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    process ( btrig_counter , short_long_sample_q )
begin
if btrig_counter = "11" then
short_long_sample_q <= not short_long_sample_q ;
end if ;
end process ;

    you have combinatorial loop. Avoid it. add Sys_clk and rewrite equation, after clock willbe added ,for short_long_sample_q you should assign when btrig_counter = 3

    also define btrig_counter as integer range 0 to 3; if it applicable. 

    process ( btrig_synched )
begin
if rising_edge ( btrig_synched ) then
btrig_counter <= btrig_counter + 1 ;
end if ;
end process ;

    it is better to have synchronus counter with sys_clk and btrig_synch as synchonous load signal 

    process ( SYS_CLK )
begin
if rising_edge ( SYS_CLK ) then
temp_pulse <= BTRIG ;
btrig_synched <= temp_pulse ;
end if ;
end process ;
process ( btrig_synched )
begin
if rising_edge ( btrig_synched ) then
btrig_counter <= btrig_counter + 1 ;
end if ;
end process ;

    and in the pair you can try better to make Pulse-Out generator . You simply get it.

    But yes do some arrangment in frequency until you get "0".