process ( btrig_counter , short_long_sample_q )
begin
if btrig_counter = "11" then
short_long_sample_q <= not short_long_sample_q ;
end if ;
end process ;
you have combinatorial loop. Avoid it. add Sys_clk and rewrite equation, after clock willbe added ,for short_long_sample_q you should assign when btrig_counter = 3
also define btrig_counter as integer range 0 to 3; if it applicable.
process ( btrig_synched )
begin
if rising_edge ( btrig_synched ) then
btrig_counter <= btrig_counter + 1 ;
end if ;
end process ;
it is better to have synchronus counter with sys_clk and btrig_synch as synchonous load signal
process ( SYS_CLK )
begin
if rising_edge ( SYS_CLK ) then
temp_pulse <= BTRIG ;
btrig_synched <= temp_pulse ;
end if ;
end process ;
process ( btrig_synched )
begin
if rising_edge ( btrig_synched ) then
btrig_counter <= btrig_counter + 1 ;
end if ;
end process ;
and in the pair you can try better to make Pulse-Out generator . You simply get it.
But yes do some arrangment in frequency until you get "0".
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