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Altera_Forum's avatar
Altera_Forum
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10 years ago

VHDL Help Requested

Hello. I'm a VHDL newbie and request help on coding a counter. I'm trying to synchronize a BTRIG signal to the system clock and then toggle a short_long_sample_q signal every 4 synchronized BTRIG pul...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Hello

In your code the process controlling short_long_sample_q is asynchronous, which means that it will keep toggling this signal until btrig_counter is different than "11". This is possibly why you are experiencing strange behaviors.

Make sure that SYSCLK > 2*BTRIG or else you will not be able to detect a rising edge on this signal

I didn't test this code, but you can give it a try: 

process ( SYS_CLK )
begin
if rising_edge ( SYS_CLK ) then
    if (btrig_previous = '0') and (BTRIG = '1') then -- Rising edge detected
         if (btrig_counter = "11") then -- Fourth rising edge detected
                  short_long_sample_q <= not short_long_sample_q;
                  btrig_counter <= "00";
         else 
                  btrig_counter <= btrig_counter + 1;
         end if
    end if
    btrig_previous <= BTRIG;
end if
end process