Heres what I have as of now, still getting a decent amound of errors and I'm having trouble dealing with two enables and I'm not really sure how to treat the hold function. Any help is greatly appreciated.
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-- Company:
-- Engineer:
--
-- Create Date: 13:38:57 11/24/2012
-- Design Name:
-- Module Name: Counter_2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Counter_2 is
Port ( E1 : in STD_LOGIC;
E2 : in STD_LOGIC;
Clk : in STD_LOGIC;
Hold : in STD_LOGIC_VECTOR (1 downto 0);
Reset : in STD_LOGIC;
Out_H : out STD_LOGIC;
Out_L : out STD_LOGIC);
end Counter_2;
architecture Behavioral of Counter_2 is
signal clk_temp1 : std_logic;
signal clk_temp2 : std_logic;
signal count : integer range 0 to 10000 := 0;
signal enable : std_logic;
begin
enable <= E1 and E2;
process (clk, reset, count, hold)
begin
if (reset = '1') then
clk_temp1 <= '0';
clk_temp2 <= '0';
count <= 0;
elsif (clk ='1' and clk'event) then
if (hold = '1') then
count <= count+1;
else
if (count = 1) then
clk_temp1 <= not clk_temp1;
clk_temp2 <= not clk_temp2;
count <= 0;
end if;
if (rising_edge(enable)) then
count <= 10000;
elsif (rising_edge(clk)) then
if count > 0 then
Out_H <= '1';
Out_L <= '0';
count <= count -1;
elsif count = 0 then
Out_H <= '0';
Out_L <= '1';
end if;
end if;
end if;
end if;
end process;
Out_H <= clk_temp1;
Out_L <= clk_temp2;
end Behavioral;
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