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Altera_Forum's avatar
Altera_Forum
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13 years ago

VHDL Help for Counter

I have to make a counter and I'm a little bit lost, any help is appreciated! variables: inputs: Enable - 2 bit vector Clock - 1 bit - 1000 Hz. Hold - 2 bit vector Reset - 1 bit outputs...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

what errors are you getting?

Plus I notice this appears to have been generated using a Xilinx template - you realise this is an Altera Forum?