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nadav12_batito's avatar
nadav12_batito
Icon for New Contributor rankNew Contributor
2 years ago
Solved

vhdl error

i neep to plan counter bcd library ieee; use ieee.std_logic_1164.all; entity h145 is port ( resetn: in std_logic; clk: in std_logic; sclear: in std_logic; cep, cet: in std_logic; qout: buff...
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  • roeekalinsky's avatar
    roeekalinsky
    2 years ago

    Looks like you're trying to synthesize your test bench, which makes no sense. Are you trying to synthesize or simulate? The test bench is for simulation only. Whereas for synthesis the top level should be entity h145 without the test bench.

RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

Thank you for acknowledging the solution provided. I'm pleased to know that your question has been addressed.


Now, I will transition this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out.

Thank you and have a great day!


Best Regards,

Richard Tan