Quartus software is not a simulator tool so you should Not compile testbench using it. Use the Questa Intel FPGA edition software or other third party simulator to compile the testbench.
Quartus is primarily used for synthesizing, fitting, and generating programming files (like bitstreams) for FPGA devices.
library ieee;
use ieee.std_logic_1164.all;
entity h145 is
port (
resetn: in std_logic;
clk: in std_logic;
sclear: in std_logic;
cep, cet: in std_logic;
qout: buffer integer range 0 to 7
);
end entity h145;
architecture are_h145 of h145 is
signal r: std_logic;
begin
process (clk)
begin
r <= cep and cet;
if resetn = '0' then
qout <= 0;
elsif resetn = '1' and sclear = '1' then
qout <=0;
elsif resetn = '1' and sclear = '1' and r = '1' then
qout <= qout+1 ;
else
qout <= qout;
end if;
end process;
end architecture are_h145;
As what @roeekalinsky mentioned, the code above (entity h145) is synthesizable. The testbench code (entity h145_tb) is not synthesizable and should Not be compiled using Quartus.
Questa Intel FPGA Edition Simulation Flow Reference:
Lite/Standard Edition:
https://www.intel.com/content/www/us/en/docs/programmable/703090/21-1/simulation-quick-start.html
Pro Edition:
https://www.intel.com/content/www/us/en/docs/programmable/691278/current.html
Regards,
Richard Tan
New Contributor
